The Mitra product line is born in 1971 within CII (Compagnie
Industrielle pour l'Informatique) as a process control computer. It was produced by the
DPOAS division, neither part of "Plan Calcul" product nor involved in Unidata.
It was targeted to replace the small process control computer CII 10010.
When in 1975, CII was absorbed by the Honeywell-Bull, its activities were not transferred to CII-HB but to another subsidiary of Thomson-CSF, created at that occasion, Société Européenne de Mini-Informatique et de Systèmes (SEMS). Mitra minicomputers were manufactured at Crolles' plant in the Grenoble area.
Between 1975 and 1982, the continuation of the Mitra line was done by SEMS (engineering in Louveciennes-Villages, manufacturing by Thomson in Crolles.
In 1982, when the big industrial groups (including CII-HB and
Thomson)were nationalized, SEMS was absorbed in Groupe Bull at French government demand.
Obviously, the Mitra product line was in competition with Honeywell Level 6.
SEMS entered the "Groupement d'Informatique Distribuée" of Bull that isolated the product lines independent from Honeywell. And the Groupe Bull added to its offering the Mitra (and Solar) product lines, targeting them towards the process control market that Level 6 did not penetrate significantly.
A couple of years later, the SEMS activities (including manufacturing) were regrouped in Echorolles-Grenoble where the other process control computer Solar (inherited from Télémécanique) had been developed.
Mitra was a 16-bits minicomputer. Its modularity was used to adapt the configuration, the peripherals and the software for each application of each customer.
Mitra processor complex instructions were interpreted by microprograms from a fast control store.
Data types referenced by instructions were: bytes, words, double words and byte strings.
Instructions could address 64 registers of 16 bits used as accumulator, accumulator extension, instruction counter, index and base registers.
Operands could be addressed as immediate, indexed, indirect.
There were 32 levels of interrupts, processed with or without program context change or with microprograms context change. Time to process an interrupt (on Mitra 15-35( varied respectively from 3 µs to 30 and 300 µs.
Input-Output operations could be under program control, asynchronous by program interrupts, asynchronous under microprogram control (450 KBps) or direct memory access (2.5MBps)
The first Mitra were developed inside CII as "Gamme Q". It was introduced as real time computers on the process control market, but also as scientific minicomputers and teleprocessing.The Mitra was used as a front-end processor for the Iris product line.
The Q-line had a TTL logic and the memory technology was magnetic core
(with an access time of 400 nanoseconds.
The main cabinet regroups a complete system with up to 32 K words and 18 peripheral adapters. The control store used bipolar technology and had a capacity from 512 to 4096 words of 16 bits. Bipolar technology registers had an access time of 60 ns.
The first model of the Mitra product line was introduced in 1971 as Mitra 15-20. It was joined by Mitra 15-21, Mitra 15-35 and the more powerful Mitra 125.
The performances of Mitra 15 operations on 16-bits were the following
Mitra 125's memory had an access time of 350 ns. It featured up to 3 microprogrammed I/O processors on the system bus. The magnetic core memory had a capacity from 16 to 512 K words and included a memory protection at the word level. The number of registers was extended to 256 words of 16-bits.
The performances of Mitra 125 operations were the following:
The I/O throughput was up to 2.2 MBps per IOP.
Up to 16 Mitra 125 could be interconnected in a multi computer operation.
The "Gamme Q" was sold until 1980 by SEMS.
There was also a military version called Mitra 15M that was sold by the Thomson-CSF parent company.
In 1977, a new line was introduced by SEMS . It was based on a new technology using VLSI Macrocells. The following models are part of "Gamme S": Mitra 115, Mitra 225, Mitra 525, Mitra 625, Mitra 725.
The Mitra 115 offered a choice of either a magnetic core memory (that could its content when not powered) or a MOS memory.
Control store of Mitra 115 was 2K words of 32-bits in ROM technology.
IOPs use DMA access at a maximum rate of 1.15 M words per second.
The performances of Mitra 225 were around those of Mitra 115. The adding time of M525 was 580 ns and that of Mitra 625/725 was 460 ns.
Mitra 525/625/725 allowed the connection of 3 I/O buses with a burst mode at 14MBps (or 17MBps on 725).
The Mitra 525 and 625 had a 8 K words of 230ns memory cache. Mitra 725 cache was 16 K words.
The higher model Mitra 725 had an extended memory capacity of 2 M words (4 MB)
Magnetic Tapes (max: 16)
Hard discs (max: 16)
The Copernique DIRAM feature has been also used on Mitra. DIRAM included a disc cache and an electronic discs and allowed the connection of SMD discs. DIRAM was a RAID-1 controller with duplication of data.
The Mitra was also the base of the New Network Architecture
developed by CII in 1971-1976. The system (hardware and software) used as a Front-End
processor was called MCR (first Mitra 15 version) and MCR-2 (based on Mitra 125).
NNA was based on proprietary protocols TMM-VU (Iriscope 300 display terminals), TMM-RB (remote batch) and TMM-UC (computer to computer links)
A total of 7,929 systems have been manufactured between 1971 and 1985. The great majority of them was sold in France. A small number (180) have been sold internationally (Benelux, Spain, USSR, Indonesia and Australia). A license to produce Mitra computers was also granted to Videoton of Hungary.
Revision : 18 novembre 2003.